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Features
* Advanced, High-speed, Electrically-erasable Programmable Logic Device
- Superset of 22V10 - Enhanced Logic Flexibility - Backward Compatible with ATV750B/BL and ATV750/L Low-power Edge-sensing "L" Option with 1 mA Standby Current D- or T-type Flip-flop Product Term or Direct Input Pin Clocking for Flip-flop 7.5 ns Maximum Pin-to-pin Delay with 5V Operation Highest Density Programmable Logic Available in 24-pin and 28-pin Packages - Advanced Electrically-erasable Technology - Reprogrammable - 100% Tested Increased Logic Flexibility - 42 Array Inputs, 20 Sum Terms and 20 Flip-flops Enhanced Output Logic Flexibility - All 20 Flip-flops Feed Back Internally - 10 Flip-flops are also Available as Outputs Programmable Pin-keeper Circuits Dual-in-line and Surface Mount Package in Standard Pinouts Full Military, Commercial and Industrial Temperature Ranges 20-year Data Retention 2000V ESD Protection 1000 Erase/Write Cycles Green Package Options (Pb/Halide-free/RoHS Compliant) Available
* * * * *
* *
High-speed Complex Programmable Logic Device ATF750C ATF750CL
* * * * * * *
1. Block Diagram
(OE PRODUCT TERMS)
12 INPUT PINS
PROGRAMMABLE INTERCONNECT AND COMBINATORIAL LOGIC ARRAY
4 TO 8 PRODUCT TERMS
LOGIC OPTION
(UP T0 20 FLIP-FLOPS)
OUTPUT OPTION
10 I/O PINS
(CLOCK PIN)
0776L-PLD-11/08
2. Pin Configurations
Pin CLK IN I/O GND VCC Function Clock Logic Inputs Bi-directional Buffers Ground +5V Supply
2.1
DIP/SOIC/TSSOP
CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN
2.2
PLCC/LCC
IN IN CLK/IN VCC(1) VCC I/O I/O 4 3 2 1 28 27 26
Note:
For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22.
3. Description
The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform predictable delays guarantee fast in-system performance. The ATF750C(L) is a high-performance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel's proven electricallyerasable technology. Each of the ATF750C(L)'s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. The ATF750CL is a low-power device with speeds as fast as 15 ns. The ATF750CL provides the optimum low-power CPLD solution. This device significantly reduces total system power, thereby allowing battery-powered operations. 2
ATF750C(L)
0776L-PLD-11/08
IN IN GND GND(1) IN I/O I/O
12 13 14 15 16 17 18
IN IN IN GND(1) IN IN IN
5 6 7 8 9 10 11
25 24 23 22 21 20 19
I/O I/O I/O GND(1) I/O I/O I/O
ATF750C(L)
4. Absolute Maximum Ratings*
Temperature Under Bias................................ -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note:
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.
5. DC and AC Operating Conditions
All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to be either 2.7V to 3.6V, 5V 5% or 5V 10%.
Commercial -7.5, -10, -15 0C - 70C 5V 5% Industrial -10, -15 -40C - +85C 5V 10%
5V Operation Operating Temperature (Ambient) VCC Power Supply
Military -55C - +125C (case) 5V 10%
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6. Logic Options
Combinatorial Output
Combined Terms Separate Terms
Registered Output
Combined Terms Separate Terms
7. Clock Mux
CKMUX CKi CLOCK PRODUCT TERM CLK PIN TO LOGIC CELL SELECT
8. Output Options
4
ATF750C(L)
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ATF750C(L)
9. Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF750C(L) have programmable "pin-keeper" circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. Please refer to the software compiler table for more details. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os.
10. Input Diagram
VCC
INPUT 100K
ESD PROTECTION CIRCUIT
PROGRAMMABLE OPTION
11. I/O Diagram
VCC
OE
DATA
I/O
VCC
100K
PROGRAMMABLE OPTION
5
0776L-PLD-11/08
12. DC Characteristics
Symbol ILI ILO Parameter Input Load Current Output Leakage Current Condition VIN = -0.1V to VCC + 1V VOUT = -0.1V to VCC + 0.1V Com. C-7, -10 Ind., Mil. ICC Power Supply Current, Standby VCC = Max, VIN = Max, Outputs Open Com. C-15 Ind., Mil. Com. CL-15 Ind. IOS(1) VIL VIH Output Short Circuit Current Input Low Voltage Input High Voltage IOL = 16 mA VOL Output Low Voltage Output High Voltage VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min IOL = 12 mA IOL = 24 mA VOH Note: IOH = -4.0 mA Com., Ind. Mil. Com. 2.4 VOUT = 0.5V 4.5 VCC 5.5V -0.6 2.0 0.15 2 -120 0.8 VCC + 0.75 0.5 0.5 0.8 mA mA V V V V V V 135 0.12 190 1 mA mA 135 125 190 180 mA mA 125 Min Typ Max 10 10 180 Units A A mA
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
13. Input Test Waveforms and Measurement Levels
tR, tF < 3 ns (10% to 90%)
14. Output Test Load
VCC 300 (390 MIL.)
390 (750 MIL.)
6
ATF750C(L)
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ATF750C(L)
15. AC Waveforms, Product Term Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
16. AC Characteristics, Product Term Clock(1)
-7
Symbol Parameter
-10 Max 7.5 7.5 7.5 Min Max 10 10 10 4 4 4 4 2 11 5.5 95 125 142 71 86 90 10 10 8 12 7 10 7.5
C/CL-15 Min Max 15 15 15 5 5 8/12 7 5 14 7 50/41 62 71 15 15 15 8 12 9 Units ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
Min
tPD tEA tER tCO tCF tS tSF tH tP tW
Input or Feedback to Non-registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tS + tCO) 3 1 3 3 1 7 3.5
7.5 5
fMAX
Internal Feedback 1/(tSF + tCF) No Feedback 1/(tP)
tAW tAR tAP tSP Note:
Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset Setup Time, Synchronous Preset 1. See ordering information for valid part numbers.
5 3
4
7
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17. AC Waveforms, Input Pin Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
18. AC Characteristics, Input Pin Clock
-7 Symbol tPD tEA tER tCOS tCFS tSS tSFS tHS tPS tWS Parameter Input or Feedback to Non-registered Output Input to Output Enable Input to Output Disable Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Period Clock Width External Feedback 1/(tSS + tCOS) fMAXS Internal Feedback 1/(tSFS + tCFS) No Feedback 1/(tPS) tAW tARS tAP tSPS Asynchronous Reset Width Asynchronous Reset Recovery Time Asynchronous Reset to Registered Output Reset Setup Time, Synchronous Preset 5 5 5 8 5/9 0 0 4 4 0 7 3.5 95 133 142 10 10 10 11 Min Max 7.5 7.5 7.5 6.5 3.5 0 0 5 5 0 10 5 83 100 100 15 15 15 Min -10 Max 10 10 10 7 5 0 0 8/12.5 7 0 12 6 55/44 80 83 C/CL-15 Min Max 15 15 15 10 5.5 Units ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns
8
ATF750C(L)
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ATF750C(L)
19. Functional Logic Diagram ATF750C, Upper Half
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20. Functional Logic Diagram ATF750C, Lower Half
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ATF750C(L)
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ATF750C(L)
21. Power-up Reset
The registers in the ATF750C(L)s are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock terms or pin high, and 3. The clock pin, or signals from which clock terms are derived, must remain stable during tPR.
Parameter tPR VRST
Description Power-up Reset Time Power-up Reset Voltage
Typ 600 2.0
Max 1000 4.5
Units ns V
22. Pin Capacitance
f = 1 MHz, T = 25C(1)
Typ CIN COUT Note: 5 6 Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
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23. Using the ATF750C's Many Advanced Features
The ATF750C(L)'s advanced flexibility packs more usable gates into 24 pins than any other logic device. The ATF750C(L)s start with the popular 22V10 architecture, and add several enhanced features: * Selectable D- and T-type Registers Each ATF750C(L) flip-flop can be individually configured as either D- or T-type. Using the Ttype configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. * Selectable Asynchronous Clocks Each of the ATF750C(L)'s flip-flops may be clocked by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. * A Full Bank of Ten More Registers The ATF750C(L) provides two flip-flops per output logic cell for a total of 20. Each register has its own sum term, its own reset term and its own clock term. * Independent I/O Pin and Feedback Paths Each I/O pin on the ATF750C(L) has a dedicated input path. Each of the 20 registers has its own feedback terms into the array as well. This feature, combined with individual product terms for each I/O's output enable, facilitates true bi-directional I/O design.
24. Synchronous Preset and Asynchronous Reset
One synchronous preset line is provided for all 20 registers in the ATF750C(L). The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flip-flops are reset when the input signals received force the internal resets high.
25. Software Support
All family members of the ATF750C(L) can be designed with Atmel(R)-WinCUPL. Additionally, the ATF750C may be programmed to perform the ATV750(L) functional subset (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV750 JEDEC file. In this case, the ATF750C becomes a direct replacement or speed upgrade for the ATV750. The ATF750C is a direct replacement for the ATV750(L) and the ATV750B(L).
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ATF750C(L)
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ATF750C(L)
26. Software Compiler Mode Selection
Table 26-1. Software Compiler Mode Selection
Atmel - WinCupL Device Mnemonic V750C V750CPPK V750LCC V750CPPKLCC Pin-keeper Disabled Enabled Disabled Enabled Device ATF750C-DIP ATF750C-PLCC
27. Third Party Programmer Support
Table 27-1.
Device
Third Party Programmer Support
Description V750 Cross-programming. JEDEC file compatible with standard V750 JEDEC file (total fuses in JEDEC file = 14394). The Programmer will automatically program "0"s into the User Rrow (UES), and disable the Pin-keeper features. The Fuse Checksum will be the same as the old ATV750/L file. This device type is recommended for customers that are directly migrating from an ATV750/L device to an ATF750C/CL device. V750B Cross-programming. JEDEC file compatible with standard V750B JEDEC file (total fuses in JEDEC file = 14435). The Programmer will automatically program "0"s into the User Row (UES), and disable the Pin-keeper feature. The Fuse Checksum will be the same as the old ATV750B/BL file. This device type is recommended for customers that are directly migrating from an ATV750B/BL device to an ATF750C/CL device. Programming of User Row (UES) bits supported and Pin-keeper bit is userprogrammable. (Total fuses in JEDEC file = 14504). This is the default device type and is recommended for users that have re-compiled their source design files to specifically target the ATF750C device.
ATF750C (V750)
ATF750C (V750B)
ATF750C
Note:
1. The ATF750C has 14,504 JEDEC fuses.
28. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF750C(L) fuse patterns. Once the security fuse is programmed, all fuses will appear programmed during verify. The security fuse should be programmed last, as its effect is immediate.
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0776L-PLD-11/08
29. Preload of Registered Outputs
The ATF750C(L)'s registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the I/O pin will force the register high; a VIL will force it low, independent of the output polarity. The PRELOAD state is entered by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock term is pulsed high, the data on the I/O pins is placed into the register chosen by the select pin .
Level Forced on Registered Output Pin during Preload Cycle VIH VIL VIH VIL
Select Pin State Low Low High High
Register #0 State after Cycle High Low X X
Register #1 State after Cycle X X High Low
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ATF750C(L)
0776L-PLD-11/08
ATF750C(L)
ATF750C SUPPLY CURRENT VS. ATF750C SUPPLY CURRENT VS. SUPPLY VOLTAGE (TAA= 25C) SUPPLY VOLTAGE (T = 25C)
140 140 120 120 100 100 ICC (mA) ICC (mA)
ATF750CL SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25C)
160 140 120 ICC (A) 100 80 60 40 20
80 80 60 60 40 40 20 20 00 4.50 4.50
4.75 4.75
5.00 5.00 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
5.25 5.25
5.50 5.50
0 4.50
4.75
5.00 SUPPLY VOLTAGE (V)
5.25
5.50
160
SUPPLY CURRENT VS. FREQUENCY STANDARD POWER (TA = 25C)
140 120
SUPPLY CURRENT VS. FREQUENCY LOW-POWER ("L") VERSION (TA = 25C)
120 ICC (mA)
100 ICC (mA) 80 60 40 20
80
40
0 0 5 10 25 FREQUENCY (MHz) 50 75 100
0 0 5 10 25 FREQUENCY (MHz) 50 75 100
ATF750C/CL OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V)
0 -5 -10 -15 IOH (mA)
ATF750C/CL OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25C)
0.00 -10.00 -20.00 -30.00 IOH (mA) -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 0.00
-20 -25 -30 -35 -40 -45 -50 4 4.5 5 SUPPLY VOLTAGE (V) 5.5 6
0.50
1.00
1.50
2.00
2.50 VOH (V)
3.00
3.50
4.00
4.50
5.00
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0776L-PLD-11/08
ATF750C/CL OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V)
44 43 42 41 IOL (mA)
ATF750C/CL OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25C)
140 120 100 IOL (mA) 80 60 40 20 0
40 39 38 37 36 35 34 4 4.5 5 SUPPLY VOLTAGE (V) 5.5 6
0
0.5
1
1.5
2
2.5 VOL (V)
3
3.5
4
4.5
5
ATF750C/CL OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25C)
90 80
INPUT CURRENT (uA) 30 25 20 15 10 5 0 -5 -10 -15 -20 -25
ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5V,TA = 25C)
70 60 IOL (mA) 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 0.7 0.8 0.9 1
0
0.5
1
1.5
2
2.5 3 3.5 4 INPUT VOLTAGE (V)
4.5
5
5.5
6
ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5V,TA = 25C) WITHOUT PIN-KEEPER
1.8 1.6 INPUT CURRENT (uA) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 INPUT VOLTAGE (V) INPUT CURRENT (mA) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0
ATF750C/CL INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 5V,TA = 35C)
-0.2
-0.4
-0.6
-0.8
-1
INPUT VOLTAGE (V)
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ATF750C(L)
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ATF750C(L)
30. ATF750C(L) Military Ordering Information
tPD (ns) tCOS (ns) Ext. fMAXS (MHz) Ordering Code ATF750C-10GM/883 ATF750C-10NM/883 5962-0720101MLA 5962-0720101M3A ATF750C-15GM/883 ATF750C-15NM/883 5962-0720102MLA 5962-0720102M3A Package 24D3 28L 24D3 28L 24D3 28L 24D3 28L Operation Range
10
7
83
Military/883 (-55 C to 125 C) Class B, Fully Compliant
15
10
55
Note:
1. Special order only: TSSOP package requires special thermal management.
31. ATF750C(L) Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns) 7.5 tCOS (ns) 6.5 Ext. fMAXS (MHz) 95 Ordering Code ATF750C-7JX ATF750C-7PX ATF750C-7SX ATF750C-10JU ATF750C-10PU ATF750C-10SU ATF750C-10XU ATF750CL-15JU ATF750CL-15PU ATF750CL-15SU ATF750CL-15XU Package 28J 24P3 24S 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0 C to 70 C)
10
7
83
Industrial (-40 C to 85 C)
15
10
44
Industrial (-40 C to 85 C)
32. Using "C" Product for Industrial
To use commercial product for industrial ranges, down-grade one speed grade from the Industrial to the Commercial device (7 ns "X" = 10 ns "U") and de-rate power by 30%.
Package Type 24D3 28J 28L 24P3 24S 24X Note:
(1)
24-lead, 0.300" Wide, Non-windowed Ceramic Dual Inline Package (CerDIP) 28-lead, Plastic J-leaded Chip Carrier (PLCC) 28-pad, Non-Windowed Ceramic Leadless Chip Carrier (LCC) 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP) 1. Special order only: TSSOP package requires special thermal management.
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33. Packaging Information
33.1 24D3 - CerDIP
Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-9 Config A (Glass Sealed)
32.51(1.280) 31.50(1.240)
PIN 1
7.87(0.310) 7.24(0.285) 27.94(1.100) REF 5.08(0.200) MAX SEATING PLANE 5.08(0.200) 3.18(0.125) 2.45(0.100)BSC 1.65(0.065) 1.14(0.045) 8.13(0.320) 7.37(0.290) 0.127(0.005) MIN
1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014)
0.46(0.018) 0.20(0.008)
0~ 15 REF
10.20(0.400) MAX
10/21/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 24D3, 24-lead, 0.300" Wide. Non-windowed, Ceramic Dual Inline Package (Cerdip) DRAWING NO. 24D3 REV. B
R
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ATF750C(L)
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ATF750C(L)
33.2 28J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 12.319 11.430 12.319 11.430 9.906 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 12.573 11.582 12.573 11.582 10.922 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 28J REV. B
R
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33.3
28L - LCC
Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-4
11.68(0.460) 11.23(0.442) 2.54(0.100) 2.16(0.085)
11.68(0.460) 11.23(0.442)
PIN 1 1.40(0.055) 1.14(0.045)
1.91(0.075) 1.40(0.055)
2.41(0.095) 1.91(0.075)
INDEX CORNER
0.635(0.025) X 45 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007)
7.62(0.300) BSC
0.737(0.029) 0.533(0.021)
1.27(0.050) TYP
1.02(0.040) X 45 2.16(0.085) 1.65(0.065)
7.62(0.300) BSC
10/21/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 28L, 28-pad, Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) DRAWING NO. 28L REV. B
R
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ATF750C(L)
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ATF750C(L)
33.4 24P3 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. 2. This package conforms to JEDEC reference MS-001, Variation AF. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 31.623 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 32.131 8.255 7.112 0.559 1.651 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
6/1/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 24P3 REV. D
R
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33.5
24S - SOIC
B
D1
PIN 1 ID PIN 1
D
e
E A
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN - 0.10 10.00 7.40 15.20 0.33 0.40 0.23 NOM - - - - - - - - 1.27 BSC MAX 2.65 0.30 10.65 7.60 15.60 0.51 1.27 0.32 NOTE
A1
A A1 D D1
0 ~ 8
L1
E B L
L
L1 e
06/17/2002 2325 Orchard Parkway San Jose, CA 95131 TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 24S REV. B
R
22
ATF750C(L)
0776L-PLD-11/08
ATF750C(L)
33.6 24X - TSSOP
Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters 0.30(0.012) 0.19(0.007)
4.48(0.176) 4.30(0.169)
6.50(0.256) 6.25(0.246)
PIN 1 0.65(0.0256)BSC
7.90(0.311) 7.70(0.303) 1.20(0.047)MAX
0.15(0.006) 0.05(0.002)
0 ~ 8
0.20(0.008) 0.09(0.004) 0.75(0.030) 0.45(0.018)
04/11/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 24X REV. A
R
23
0776L-PLD-11/08
34. Revision History
Revision Level - Release Date K - July 2007 L - November 2008 History Added military-grade devices. Added fully-green RoHS-compliant devices in select speed grades and packages. Removed commercial grade leaded package options.
24
ATF750C(L)
0776L-PLD-11/08
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support pld@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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0776L-PLD-11/08

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